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uvm Jobs near Emeryville, CA

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Sr. ASIC Design Verification Engineer - UVM, PCIe, CXL
Posted 07/20/2023
San Jose, CA
Full-time
$150,000.00 - $225,000.00
Job Title: Sr. ASIC Design Verification Engineer - UVM, PCIe, CXL Job Location: San Jose, CA Compensation: $150K - $225K+ base Depending on experience plus stock options! Requirements: ASIC Design...
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  • Verification
  • PCIe
  • ASIC Design
  • UVM
  • CXL
Principal ASIC Design Verification Engineer - UVM, PCIe, CXL
Posted 09/18/2023
San Jose, CA
Full-time
$180,000.00 - $240,000.00
Job Title: Principal ASIC Design Verification Engineer - UVM, PCIe, CXL Job Location: San Jose, CA Compensation: $180K - $240K base Depending on experience plus stock options! Requirements: ASIC D...
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  • Verification
  • PCIe
  • ASIC Design
  • UVM
  • CXL
Sr. Design Verification Engineer
Posted 04/02/2025
San Jose, CA
Full-time
$150,000.00 - $230,000.00
Sr. Design Verification Engineer Position Overview We are seeking a highly skilled Sr. Design Verification Engineer to join our dynamic team. The ideal candidate will have a strong background in verif...
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  • Design Verification
  • PCIe
  • CXL
  • UVM
  • System Verilog
Verification Engineer
Posted 01/29/2025
San Jose, CA
Full-time
$150,000.00 - $175,000.00
We are a well established semiconductor company focuseed in the area of SSD memory and IC solutions. As we grow we are looking to add to our team with a new Verification with experience in the verific...
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  • UVM
  • SOC
  • PCIe
  • Python
  • Systems Verilog
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Staff R&D IC Design Verification Engineer (up to 350k pkg!)
Posted 04/29/2025
San Jose, CA
Full-time
$140,000.00 - $190,000.00
Role : Staff R&D Design Verification Engineer Comp : Base (140-190k) + bonus (25%) plus very generous RSUs! Total first year comp up to 350k Location : San Jose, CA (Onsite) Position Overview We are s...
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  • Verilog
  • SystemVerilog
  • UVM
  • Design Verification
  • Chip Level Design
Principal R&D IC Design Verification Engineer (up to 500k pkg!)
Posted 05/06/2025
San Jose, CA
Full-time
$180,000.00 - $225,000.00
Role : Principal R&D Design Verification Engineer Comp : Base (up to 225k) + bonus (30%) plus very generous RSUs! Total first year comp up to $500k Location : San Jose, CA (Onsite) Position Overview W...
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  • Verilog
  • SystemVerilog
  • UVM
  • Design Verification
  • Chip Level Design
 
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